Buffalo NAS-Central Forums

Welcome to the Linkstation Wiki community
It is currently Wed Aug 15, 2018 1:49 am

All times are UTC+01:00




Post new topic  Reply to topic  [ 9 posts ] 
Author Message
PostPosted: Wed Feb 01, 2017 5:14 am 
Offline
Newbie
User avatar

Joined: Tue Nov 01, 2016 1:17 pm
Posts: 45
http://buffalo.nas-central.org/wiki/Linkstation_400#Serial_Console

Image
Full image http://images.vfl.ru/ii/1485922363/1814 ... 907576.jpg

LS410
Image
Full image http://www.yamasita.jp/linkstation/2013/07/130729_2.jpg

Image
Full image http://www.yamasita.jp/linkstation/2013/07/130729_1.jpg

LS421
Image
Full image http://images.vfl.ru/ii/1486459011/7599 ... 993311.jpg

Image
Full image http://images.vfl.ru/ii/1486459156/8688 ... 993330.jpg


Top
   
PostPosted: Wed Feb 08, 2017 9:18 pm 
Offline
Newbie
User avatar

Joined: Tue Nov 01, 2016 1:17 pm
Posts: 45
FW 1.81 LS421DE w/o disks

Code:
BootROM 1.08
Booting from SPI flash


General initialization - Version: 1.0.0
mvBoardSerdesModulesScan: mvTwsiRead error, Using default serdes configuration ****
High speed PHY - Version: 2.1.4 (COM-PHY-V20)
Update PEX Device ID 0x67100
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.1

DDR3 Training Sequence - Run DDR3 at 600 Mhz

########### LOG LEVEL 1 (D-UNIT SETUP)###########

Static D-UNIT Setup:
0x00001400 = 0x73014924
0x00001404 = 0x3000B808
0x00001408 = 0x56159996
0x0000140C = 0x3AD93F96
0x00001410 = 0x120F0000
0x00001414 = 0x00000000
0x00001418 = 0x00000E00
0x0000141C = 0x00000642
0x00001420 = 0x00000004
0x00001424 = 0x0100F37F
0x00001428 = 0x000F8830
0x00001454 = 0x00000000
0x00001474 = 0x00000000
0x0000142C = 0x014C4EE4
0x0000147C = 0x0000C671
0x00001494 = 0x00010000
0x00001498 = 0x00000000
0x0000149C = 0x0000030F
DDR3 Training Sequence - Run without PBS.
Cuurrent frequency is: 100MHz
Cuurrent frequency is: 444MHz
DDR3 - Write Leveling - Starting HW WL procedure
DDR3 - Write Leveling - Write Leveling Cs - 0 Results:
DDR3 - Write Leveling - PUP: 0, Phase: 0, Delay: 03
DDR3 - Write Leveling - PUP: 1, Phase: 0, Delay: 07
DDR3 - Write Leveling - HW WL Ended Successfully
DDR3 - Read Leveling - Starting HW RL procedure
DDR3 - Read Leveling - Results for CS - 0
DDR3 - Read Leveling - PUP: 0, Phase: 1, Delay: 1F
DDR3 - Read Leveling - PUP: 1, Phase: 2, Delay: 02
DDR3 - Read Leveling - Read Sample Delay: 09
DDR3 - Read Leveling - Read Ready Delay: 0D
DDR3 - Read Leveling - HW RL Ended Successfully
DDR3 - Write Leveling Hi-Freq Supplement - Starting
DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled
COUNT = 0
DATA PUP:
04030201 08070605 0C0B0A09 100F0E0D
14131211 18171615 1C1B1A19 201F1E1D
24232221 28272625 2C2B2A29 302F2E2D
34333231 38373635 3C3B3A39 403F3E3D
44434241 48474645 4C4B4A49 504F4E4D
54535251 58575655 5C5B5A59 605F5E5D
64636261 68676665 6C6B6A69 706F6E6D
74737271 78777675 7C7B7A79 807F7E7D
CS: 0 PUP: 0
Actual Data = 21
Expected Data = 21
uiError = 00
uiErrorN = 00

CS: 0 PUP: 1
Actual Data = 22
Expected Data = 22
uiError = 00
uiErrorN = 00
COUNT = 1
DATA PUP:
04030201 08070605 0C0B0A09 100F0E0D
14131211 18171615 1C1B1A19 201F1E1D
24232221 28272625 2C2B2A29 302F2E2D
34333231 38373635 3C3B3A39 403F3E3D
44434241 48474645 4C4B4A49 504F4E4D
54535251 58575655 5C5B5A59 605F5E5D
64636261 68676665 6C6B6A69 706F6E6D
74737271 78777675 7C7B7A79 807F7E7D
CS: 0 PUP: 0
Actual Data = 21
Expected Data = 21
uiError = 00
uiErrorN = 00

CS: 0 PUP: 1
Actual Data = 22
Expected Data = 22
uiError = 00
uiErrorN = 00
DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully

########## LOG LEVEL 3(Windows margins per-DQ) ##########
DDR3 - RX  CS: 0

DATA RESULTS:

BYTE:0
  DQ's        LOW       HIGH       WIN-SIZE
============================================
DQ[ 0]     0x41       0x2D       0xED
DQ[ 1]     0x33       0x2F       0xFD
DQ[ 2]     0xE8       0x4B       0x64
DQ[ 3]     0x01       0xFA       0xFA
DQ[ 4]     0x59       0xFE       0xA6
DQ[ 5]     0x9A       0xE5       0x4C
DQ[ 6]     0x6F       0x03       0x95
DQ[ 7]     0x3B       0xAD       0x73

BYTE:1
  DQ's        LOW       HIGH       WIN-SIZE
============================================
DQ[ 8]     0x5D       0x9D       0x41
DQ[ 9]     0x4E       0x0D       0xC0
DQ[10]     0xC7       0x79       0xB3
DQ[11]     0x41       0x01       0xC1
DQ[12]     0xE2       0x40       0x5F
DQ[13]     0x7A       0x86       0x0D
DQ[14]     0xFA       0xC7       0xCE
DQ[15]     0x20       0x08       0xE9


############ LOG LEVEL 2(Windows margins) ############
DDR3 - DQS RX - Set Dqs Centralization Results - CS: 0

DQS    LOW     HIGH     WIN-SIZE      Set
==============================================
0     0x00      0x1A      0x1A       0x0D
1     0x00      0x1B      0x1B       0x0D

########## LOG LEVEL 3(Windows margins per-DQ) ##########
DDR3 - TX  CS: 0

DATA RESULTS:

BYTE:0
  DQ's        LOW       HIGH       WIN-SIZE
============================================
DQ[ 0]      0x2E        0x41        0x13
DQ[ 1]      0x30        0x33        0x03
DQ[ 2]      0x4C        0xE8        0x9C
DQ[ 3]      0xFB        0x01        0x06
DQ[ 4]      0xFF        0x59        0x5A
DQ[ 5]      0xE6        0x9A        0xB4
DQ[ 6]      0x04        0x6F        0x6B
DQ[ 7]      0xAE        0x3B        0x8D

BYTE:1
  DQ's        LOW       HIGH       WIN-SIZE
============================================
DQ[ 8]      0x9E        0x5D        0xBF
DQ[ 9]      0x0E        0x4E        0x40
DQ[10]      0x7A        0xC7        0x4D
DQ[11]      0x02        0x41        0x3F
DQ[12]      0x41        0xE2        0xA1
DQ[13]      0x87        0x7A        0xF3
DQ[14]      0xC8        0xFA        0x32
DQ[15]      0x09        0x20        0x17


############ LOG LEVEL 2(Windows margins) ############
DDR3 - DQS TX - Set Dqs Centralization Results - CS: 0

DQS    LOW     HIGH     WIN-SIZE      Set
==============================================
0     0x00      0x1B      0x1B       0x0D
1     0x00      0x1B      0x1B       0x0D
DDR3 Training Sequence - Ended Successfully
BootROM: Image checksum verification PASSED

____                            _
| __ )  _   _  ___   ___   ___  | |  ___
|  _  \| | | |/   | /   | / _  \| | / _  \
| |_) || |_| ||  __||  __| (_) || || (_) |
|____/  \___/ |_|   |_|   \__/|||_| \___/
         _   _     ____                _
        | | | |   | __ )   ___   ___  | |_
        | | | |___|  _  \ / _  \/ _  \| __|
        | |_| |___| |_) || (_) | (_) || |_
         \___/    |____/  \___/ \___/  \__|
** LOADER **


U-Boot 2011.12 (Jan 15 2015 - 21:22:47) Marvell version: v2011.12 2014_T2.0p1

Board: YANAGI
BoardID= 0
SoC:   MV6710 A1
CPU:   Marvell PJ4B v7 UP (Rev 1) LE
       CPU    @ 1200 [MHz]
       L2     @ 600 [MHz]
       TClock @ 200 [MHz]
       DDR    @ 600 [MHz]
       DDR 16Bit Width, FastPath Memory Access
DRAM:  512 MiB
PHY ID = 1d
PHY ID = 1d

Map:   Code:            0x1ff0d000:0x1ffa2b68
       BSS:             0x1ffefaa4
       Stack:           0x1f9fcef8
       Heap:            0x1f9fd000:0x1ff0d000

NAND:  512 MiB
MMC:   MRVL_MMC: 0
SF: Detected MX25L8005 with page size 64 KiB, total 1 MiB

Initialize and scan all PCI interfaces
PEX unit.port(active IF[-first bus]):
------------------------------------------
PEX 0: Root Complex Interface, Detected Link X1, GEN 1.1
PEX 0.1(1): Detected No Link.
u-boot envinit tval=f24c458d
FPU initialized to Run Fast Mode.
USB 0: Host Mode
USB 1: Host Mode
Modules/Interfaces Detected:
       RGMII0 Phy
       RGMII1 Phy
       PEX0 (Lane 0)
       PEX1 (Lane 1)
       SATA0 (Lane 2)
       SATA1 (Lane 3)
USB Power ON

Marvell Serial ATA Adapter
Integrated Sata device found

MAC Address : 10:6F:3F:XX:XX:XX
Net:   egiga0, egiga1 [PRIME]
hit any key to switch tftp boot.
Hit any key to stop autoboot:  0


Code:
BUFFALO>> help
?       - alias for 'help'
SatR    - Sample At Reset sub-system

active_units- print Board units active
base    - print or set address offset
bdinfo  - print Board Info structure
boot    - boot default, i.e., run 'bootcmd'
bootd   - boot default, i.e., run 'bootcmd'
bootelf - Boot from an ELF image in memory
bootfail- - boot image not found. press func sw to continue .

bootm   - boot application image from memory
bootp   - boot image via network using BOOTP/TFTP protocol
bootvx  - Boot vxWorks from an ELF image
bootz   - boot Linux zImage image from memory
bubt    - bubt  - Burn an image on the Boot Flash.

chpart  - change active partition
cmp     - memory compare
coninfo - print console devices and information
cp      - memory copy
crc32   - checksum calculation
date    - get/set/reset date & time
dcache  - enable or disable data cache
ddrPhyRead- ddrPhyRead - Read DDR PHY register

ddrPhyWrite- ddrPhyWrite - Write DDR PHY register

dhcp    - boot image via network using DHCP/TFTP protocol
diskboot- diskboot- boot from IDE device

dma     - dma   - Perform DMA using the XOR engine

echo    - echo args to console
editenv - edit environment variable
eeprom  - EEPROM sub-system
env     - environment handling commands
exit    - exit script
ext2load- load binary file from a Ext2 filesystem
ext2ls  - list files in a directory (default /)
false   - do nothing, unsuccessfully
fatIsSettingInitializeDisk- Check if it is a setting initialize disk or not.
fatIsSettingRecoveryDisk- Check if it is a setting recovery disk or not.
fatinfo - print information about filesystem
fatload - load binary file from a dos filesystem
fatls   - list files in a directory (default /)
fsinfo  - print information about filesystems
fsload  - load binary file from a filesystem image
go      - start application at address 'addr'
help    - print command description/usage
i2c     - I2C sub-system
icache  - enable or disable instruction cache
ide     - ide     - IDE sub-system

iminfo  - print header information for application image
imxtract- extract a part of a multi-image
ir      - ir    - reading and changing MV internal register values.

itest   - return true/false on integer compare
loadb   - load binary file over serial line (kermit mode)
loads   - load S-Record file over serial line
loadx   - load binary file over serial line (xmodem mode)
loady   - load binary file over serial line (ymodem mode)
loop    - infinite loop on address range
ls      - list files in a directory (default /)
map     - map   - Display address decode windows

md      - memory display
me      - me    - PCI master enable

mm      - memory modify (auto-incrementing address)
mmc     - MMC sub system
mmcinfo - display MMC info
mp      - mp    - map PCI BAR

mtdparts- define flash/nand partitions
mtest   - simple RAM read/write test
mw      - memory write (fill)
nand    - NAND sub-system
nboot   - boot from NAND device
nfs     - boot image via network using NFS protocol
nm      - memory modify (constant address)
pci     - list and access PCI Configuration Space
pciePhyRead- phyRead    - Read PCI-E Phy register

pciePhyWrite- pciePhyWrite      - Write PCI-E Phy register

phyRead - phyRead       - Read Phy register

phyWrite- phyWrite      - Write Phy register

ping    - send ICMP ECHO_REQUEST to network host
poff    - - Board power off

printenv- print environment variables
pxe     - commands to get and boot from pxe files
rcvr    - rcvr  - Satrt recovery process (Distress Beacon with TFTP server)

reboot  - - Board power off

reset   - Perform RESET of the CPU
resetenv- resetenv      - Erase environment sector to reset all variables to default.

run     - run commands in an environment variable
saveenv - save environment variables to persistent storage
se      - se    - PCI Slave enable

setenv  - set environment variables
sf      - SPI flash sub-system
sg      - sg    - scanning the PHYs status

showvar - print local hushshell variables
sleep   - delay execution for some time
source  - run script from memory
sp      - scan and detect all devices on mvPCI interface
sspi    - SPI utility command
sum_check_nand- - nand checksum checking now by spi env... .

temp    - temp  - Display the device temperature.

tempCmd0- tempCmd - This command allocated for monitor extinction

tempCmd1- tempCmd - This command allocated for monitor extinction

tempCmd2- tempCmd - This command allocated for monitor extinction

tempCmd3- tempCmd - This command allocated for monitor extinction

test    - minimal test like /bin/sh
tftpboot- boot image via network using TFTP protocol
training- training      - prints the results of the DDR3 Training.

true    - do nothing, successfully
ts_report- ts_report    - report touch screen coordinate

ts_test - ts_test       - test touch screen

ubi     - ubi commands
ubifsload- load file from an UBIFS filesystem
ubifsls - list files in a directory
ubifsmount- mount UBIFS volume
ubifsumount- unmount UBIFS volume
usb     - USB sub-system
usbboot - boot from USB device
version - print monitor, compiler and linker version
whoAmI  - - reading CPU ID

BUFFALO>>


Top
   
PostPosted: Sun Jun 03, 2018 10:50 am 
Offline
Newbie

Joined: Fri Mar 21, 2008 3:04 am
Posts: 61
Thanks. But how can the main board be taken out? I got an old ls421de for me, but am still trying to figure that out.


Top
   
PostPosted: Sun Jun 03, 2018 4:01 pm 
Offline
Moderator

Joined: Mon Apr 26, 2010 10:24 am
Posts: 2734
http://forum.nas-hilfe.de/buffalo-techn ... t2629.html


Top
   
PostPosted: Mon Jun 04, 2018 2:39 pm 
Offline
Newbie

Joined: Fri Mar 21, 2008 3:04 am
Posts: 61
Thank you so much. Now I have only one question before I start to actually working on my ls421de. I posted it in another post, would you please have a look for me? I'm really confused how the system gets to start from hdd.


Top
   
PostPosted: Sat Jun 09, 2018 10:41 am 
Offline
Newbie

Joined: Fri Mar 21, 2008 3:04 am
Posts: 61
Hi Oxygen
Just got tools needed to do the work. What does the "X" on the left side of the R265 mean? Do I need to remove that resistor completely?

Another question:
Is there any correspondence between those two points of the resistors to the J11/J12 pins? Or I can just select randomly?

Regards


Top
   
PostPosted: Sat Jun 09, 2018 11:13 am 
Offline
Moderator

Joined: Mon Apr 26, 2010 10:24 am
Posts: 2734
X

do not use this


J11/J12 ?
Quote:
it looked like these signals get routed over to two 4-pin connectors (not populated) on the edge of the board (J11 and J12). But the signals didn't actually show up.

read the howto


Top
   
PostPosted: Sat Jun 09, 2018 2:17 pm 
Offline
Newbie
User avatar

Joined: Tue Nov 01, 2016 1:17 pm
Posts: 45
hato wrote:
Just got tools needed to do the work. What does the "X" on the left side of the R265 mean? Do I need to remove that resistor completely?


This means that you need to join the right of the resistor. To the left of the resistor, the signal is lost.
Join the places that are marked. Ground line from converter connect to metal chassis.

I did not solder anything, just pinned the contacts to these places.


Top
   
PostPosted: Sat Jun 09, 2018 5:27 pm 
Offline
Newbie

Joined: Fri Mar 21, 2008 3:04 am
Posts: 61
Thanks Antonas (and Oxygen8).

Like I said in another topic, it's working now.

The problem was that I tried to repeat what is said on the wiki page, to jumper the signals to J11/J12. But I didn't know which pins of the J11/J12 that the TX and RX signals should connect to. The original post doesn't have information about this. In fact, for the 4 pins of J11/J12, one is ground, so I need to know which two of the other threes pins shall be connected to the TX and RX signals from besides the R265 and R106. The last one is 3.5V (but I measured around 3.2V). And the left side of R265 actually is connected directly to that 3.5V pin.
I actually made a mistake first by connect R265 to that 3.2V pins which resulted in I can read the output, but can't input anything (including pausing the start). Anyway, it's all good now. Thank you guys :up: .

Regards


Top
   
Display posts from previous:  Sort by  
Post new topic  Reply to topic  [ 9 posts ] 

All times are UTC+01:00


Who is online

Users browsing this forum: Google [Bot] and 2 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Powered by phpBB® Forum Software © phpBB Limited